The PCI-SIG Organization has announced the official release of the PCIe 6.0 specification standard v1.0, declaring completion.
Continuing the convention, the bandwidth speed continues to double, up to 128GB/s(unidirectional) at x16, and since PCIe technology allows full-duplex bidirectional data flow, the total two-way throughput is 256GB/s. According to the plan, there will be commercial examples 12 to 18 months after the publication of the standard, which is about 2023, should be on the server platform first. PCIe 6.0 will come by the end of the year at the earliest, with a bandwidth of 256GB/s
Back to the technology itself, PCIe 6.0 is considered to be the biggest change in PCIe’s nearly 20-year history. To be frank, PCIe 4.0/5.0 is a minor modification of 3.0, such as the 128b/130b encoding based on NRZ (Non-Return-to-Zero).
PCIe 6.0 switched to PAM4 pulse AM signaling, 1B-1B coding, a single signal can be four encoding (00/01/10/11) states, double the previous, allowing for up to 30GHz frequency. However, because PAM4 signal is more fragile than NRZ, it is equipped with FEC forward error correction mechanism to correct signal errors in the link and ensure data integrity
In addition to PAM4 and FEC, the last major technology in PCIe 6.0 is the use of FLIT (Flow Control Unit) encoding at the logical level. In fact, PAM4, FLIT is not a new technology, in the 200G+ ultra-high-speed Ethernet has long been applied, which PAM4 failed to large-scale promotion of the reason is that the physical layer cost is too high.
In addition, PCIe 6.0 remains backward compatible.
PCIe 6.0 continues to double the I/O bandwidth to 64GT/s according to the tradition, which is applied to the actual PCIe 6.0X1 unidirectional bandwidth of 8GB/s, PCIe 6.0×16 unidirectional bandwidth of 128GB/s, and pcie 6.0×16 bidirectional bandwidth of 256GB/s. PCIe 4.0 x4 SSDS, which are widely used today, will only need PCIe 6.0 x1 to do it.
PCIe 6.0 will continue the 128b/130b encoding introduced in the era of PCIe 3.0. In addition to the original CRC, it is interesting to note that the new channel protocol also supports the PAM-4 encoding used in Ethernet and GDDR6x, replacing PCIe 5.0 NRZ. More data can be packed in a single channel in the same amount of time, as well as a low-latency data error correction mechanism known as forward error correction (FEC) to make increasing bandwidth feasible and reliable.
Many people may question, PCIe 3.0 bandwidth is often not used up, PCIe 6.0 is what use? Due to the increase in data-hungry applications, including artificial intelligence, IO channels with faster transmission rates are increasingly becoming the demand of customers in the professional market, and the high bandwidth of PCIe 6.0 technology can fully unlock the performance of products requiring high IO bandwidth including accelerators, machine learning and HPC applications. PCI-SIG also hopes to benefit from the growing automotive industry, which is a hot spot for semiconductors, and the PCI-Special Interest Group has formed a new PCIe Technology working group to focus on how to increase the adoption of PCIe technology in the automotive industry, as the ecosystem’s increased demand for bandwidth is evident. However, as the microprocessor, GPU, IO device and data storage can be connected to the data channel, PC to obtain the support of PCIe 6.0 interface, motherboard manufacturers need to be extra careful to arrange the cable that can handle high-speed signals, and chipset manufacturers also need to make relevant preparations. An Intel spokesperson declined to say when PCIe 6.0 support will be added to devices, but confirmed that the consumer Alder Lake and server side Sapphire Rapids and Ponte Vecchio will support PCIe 5.0. NVIDIA also declined to say when PCIe 6.0 will be introduced. However, BlueField-3 Dpus for data centers already support PCIe 5.0; The PCIe Spec only specifies the functions, performance, and parameters that need to be implemented at the physical layer, but does not specify how to implement these. In other words, manufacturers can design the physical layer structure of PCIe according to their own needs and actual conditions to ensure functionality! Cable manufacturers can play more space!
Post time: Jul-04-2023
