Introduction to PCIe 5.0 specifications

• Introduction to PCIe 5.0 specifications

The PCIe 4.0 specification was completed in 2017, but it was not supported by consumer platforms until AMD’s 7nm Rydragon 3000 series, and previously only products such as supercomputing, enterprise-class high-speed storage, and network devices used PCIe 4.0 technology. Although PCIe 4.0 technology has not yet been applied on a large scale, the PCI-SIG organization has long been developing a faster PCIe 5.0, the signal rate has doubled from the current 16GT/s to 32GT/s, the bandwidth can reach 128GB/s, and the version 0.9/1.0 specification has been completed. v0.7 version of the PCIe 6.0 standard text has been sent to members, and the development of the standard is on track. The pin rate of PCIe 6.0 has been increased to 64 GT/s, which is 8 times that of PCIe 3.0, and the bandwidth in x16 channels can be larger than 256GB/s. In other words, the current speed of PCIe 3.0 x8 requires only one PCIe 6.0 channel to achieve. As far as v0.7 is concerned, PCIe 6.0 has achieved most of the features originally announced, but the power consumption is still further improved, and the standard has newly introduced the L0p power configuration gear. Of course, after the announcement in 2021, PCIe 6.0 can be commercially available in 2023 or 2024 at the earliest. For example, PCIe 5.0 was approved in 2019, and it is only now that there are application cases

Compared with the previous standard specifications, PCIe 4.0 specifications came relatively late. PCIe 3.0 specifications were introduced in 2010, 7 years after the introduction of PCIe 4.0, so the life of PCIe 4.0 specifications may be short. In particular, some vendors have begun to design PCIe 5.0 PHY physical layer devices.

The PCI-SIG organization expects the two standards to coexist for some time, and PCIe 5.0 is mainly used for high-performance devices with higher throughput requirements, such as Gpus for AI, network devices, and so on, which means that PCIe 5.0 is more likely to appear in data center, network, and HPC environments. Devices with less bandwidth requirements, such as desktops, can use PCIe 4.0.

For PCIe 5.0, the signal rate has been increased from PCIe 4.0′s 16GT/s to 32GT/s, still using 128/130 encoding, and the x16 bandwidth has been increased from 64GB/s to 128GB/s.

In addition to doubling the bandwidth, PCIe 5.0 brings other changes, changing the electrical design to improve signal integrity, backward compatibility with PCIe, and more. In addition, PCIe 5.0 has been designed with new standards that reduce latency and signal attenuation over long distances.

The PCI-SIG organization expects to complete the 1.0 version of the specification in Q1 this year, but they can develop standards, but they can’t control when the terminal device is introduced to the market, and it is expected that the first PCIe 5.0 devices will debut this year, and more products will appear in 2020. However, the need for higher speeds prompted the standard body to define the next generation of PCI Express. The goal of PCIe 5.0 is to increase the speed of the standard in the shortest possible time. Therefore, PCIe 5.0 is designed to simply increase the speed to the PCIe 4.0 standard without any other significant new features.

For example, PCIe 5.0 does not support PAM 4 signals and only includes the new features needed to enable the PCIe standard to support 32 GT/s in the shortest possible time.

Hardware challenges

The major challenge in preparing a product to support PCI Express 5.0 will be related to channel length. The faster the signal rate, the higher the carrier frequency of the signal transmitted through the PC board. Two types of physical damage limit the extent to which engineers can propagate PCIe signals:

· 1. Attenuation of channel

· 2. Reflections that occur in the channel due to impedance discontinuities in pins, connectors, through-holes and other structures.

The PCIe 5.0 specification uses channels with -36dB attenuation at 16 GHz. The frequency 16 GHz represents the Nyquist frequency for 32 GT/ s digital signals. For example, when the PCIe5.0 signal starts, it may have a typical peak-to-peak voltage of 800 mV. However, after passing through the recommended -36dB channel, any resemblance to an open eye is lost. Only by applying transmitter based equalization (de-accentuating) and receiver equalization (a combination of CTLE and DFE) can the PCIe5.0 signal pass through the system channel and be accurately interpreted by the receiver. The minimum expected eye height of a PCIe 5.0 signal is 10mV(post-equalization). Even with a near-perfect low-jitter transmitter, significant attenuation of the channel reduces the signal amplitude to the point where any other type of signal damage caused by reflection and crosstalk can be closed to restore the eye.